Technical Lead I - VLSI

• Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams
• On time quality delivery approved by the project manager and client
• Automate the design tasks flows and write scripts to generate reports
• Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client

• Timely delivery - verified using relevant metrics by UST Manager / Client Manager
• Reduction in cycle time cost using innovative approaches
• Number of papers published
• Number of patents filed
• Number of mandatory trainings attended adhering to training goals

• Clean delivery of the design/module in-terms of ease in integration at the top level
• Meeting functional spec / design guidelines 100% without any deviation or limitation
• Documentation of tasks and work performed

• Meet intermediate tasks delivery for other team members to progress
• Calling out for help and support in the case of delay in tasks delivery

• Take up new areas of project development

• Able to take up additional tasks in-case of any team member(s) not available
• Able to hand hold junior team members to explain the project tasks and support to deliver
• Work dedication to go beyond the call of duty to ensure deadlines and quality are met

• Participation on technical discussion

• EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools)
• Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
• Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
• Strong communication skills and ability to interact with team members and clients equally
• Strong analytical reasoning and problem-solving skills with attention to details
• Ability to understand the standard specs and functional documents
• Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT
• Well versed with the available EDA tools and able to use them efficiently
• Required technical skills and prior design knowledge to execute the assigned tasks
• Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project

• Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
• Understanding of the design flow and methodologies used in the designing
• Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills

• Relevant working experience between 6 - 10 Years in preferably digital Standard Cell library development. • Should fit in an industrial development environment where a combination of project driven and innovation activities generate transferable results for our business. • Should be flexible and team player. • Very analytical in nature and able to work in a multi-disciplinary environment. • Creative, out-of-the-box thinker with a high level of personal involvement. • Strong theoretical background with a pragmatic approach. • Good communication skills and fluent in English. • Scripting – Perl/Tcl/Python knowledge is a plus. • Able to work in a multi-cultural environment. Job Responsibilities • Characterization experience with different industry standard tools (Experience of generating NLDM, CCS, ECSM views with validation). Development experience of Characterization Methodology is a certain plus. • Industry standard flow methodology development experience is a certain plus. • Should have worked on Standard cells libraries especially deep Submicron, FinFET and SOI. • Take ownership for the improvement/development of circuits and Characterization of StdCell libraries. Required Qualifications • Education BTech/M-Tech in VLSI/Electronics Engineering with 5+ years of relevant experience • Fluency in English Language – written & verbal • Good interpersonal skills Job Description/Experience Requirements: • Understanding of deep submicron device physics • Characterization experience with different industry standard tools • Perform Characterization Including NLDM, CCS, AOCV, LVF and validate Standard Cell Libraries. • Expertise in Standard Cell library development including the Design, Characterization and EDA Modeling of Standard Cell libraries. • Aware of layout proximity Effects in Standard cells and impact to Power, Leakage and Performance. • Development of CMOS standard cell libraries for high speed, low power, automotive products using different foundry/process technologies. • Good debugging skill needed • Skill, Perl, Python Programming is a value add • Write and simulate behavioral Verilog models for standard cells. • Create EDA views and perform validation of library views. • Perform Library comparison and benchmarking (Power, Performance and Area) • Release Standard Cell Libraries with Quality Checks Requirements/Qualifications: • Bachelor’s degree in Electronics/Electronics & communication with a minimum of 4 years of experience in semiconductor industry. Master’s Degree is plus. • Hands on experience in Standard Cell library development with expertise in characterization. • Strong understanding of CMOS and FinFet technologies. • Exposure to Verilog Modeling is desired. • Strong debugging and problem solving skills in the areas of cell design, spice simulation and characterization. • Exposure to EDA tools like Cadence Virtuoso, Calibre, Hspice any Industry standard Simulation & Characterization tool is a must. • Programming skills using Perl, TCL and Cadence SKILL is a Plus.

UST