Assisting Front End Design and Integration Engineers with SRAM/RF specification and synthesis design constraints. In-depth technical expertise in one or more areas: Physical Synthesis, Floor-Planning, Place and Route, Power Grid, Clock Tree Synthesis, Static Timing Analysis for Partition Level and Full Chip Level Timing Closure, SRAM Compilers, Physical Design Verification (DRC/LVS), Formal Equivalence Verification (FEV), ATPG. Proficiency in writing TCL with demonstrated experience in using TCL with one or more Physical Design Tools. A solid understanding of Unified Power Format (UPF) for describing power intent. Excellent knowledge of Synthesis Design Constraints and Static Timing Analysis. Excellent understanding of clocking concepts, including asynchronous crossings and structures used to synchronize clock domain crossings. Good understanding of computer architecture concepts, including SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc. 10+ years of relevant job/skill-related experience. Experience delivering highly technical solutions. Experience in any of the following focus areas: memory array architectures, on-die and off-die high-speed signaling, PHY & interface development, power delivery network planning and optimization, power consumption reduction, CMOS requirements identification, packaging technologies, and thermal modeling.
