Design Verification Engineer
Weekday AI View all jobs
- Hyderabad, Telangana
- Permanent
- Full-time
- Establish verification testing strategies and create detailed plans
- Create and implement test plans for unit, IP, subsystem, and SoC level verification
- Design SystemVerilog test benches that include stimulus, checkers, transactors/BFMs, assertions, and coverage points
- Detect issues in architecture, functionality, and performance
- Enhance design verification methodologies and develop reusable verification frameworks
- Assist with verification efforts across module-level testing, full chip analysis, emulation, prototyping, silicon bring-up, manufacturing diagnostics, compilers, and shipping platform software
- Collaborate closely with micro-architecture and design teams
- In-depth understanding of Computer Architecture
- Practical experience with UVM, SystemVerilog, C, and C++
- Familiarity with SystemVerilog simulators and waveform debugging tools
- Proven experience in developing and executing verification plans at the Unit, IP, Subsystem, and SoC levels
- Experience in creating SystemVerilog test benches, including stimulus, checkers, transactors/BFMs, assertions, and coverage points
- Strong debugging and analytical skills in identifying bugs
- Familiarity with design and verification tools such as VCS or equivalent simulation software
- Experience with debugging tools like Debussy/DVE
- Exceptional debugging and problem-solving abilities