NAND Testchip test flow development and validation Run pre si Verilog (Digital) and Analog design simulations to verify testmodes. Perform device characterization and electrical failure analysis (EFA) Collaborate with Test Solutions Engineering on test code development. Collaborate with Design Engineering on testmode implementation, pre si verification and post si validation of testmodes. Collaborate with Process Integration, yield engineering to improve overall die yield and meet the critical milestones planned for the testchip. 6-8+ years of experience in VLSI, semiconductor industry Strong foundation of mixed-signal VLSI such as analog circuits and systems, digital logic and RTL design. Excellent data analysis, problem solving, and decision-making skills Knowledge of bench testing equipment (o-scope, logic analyzer, Nextest Magnum, etc) Fundamental programming/scripting skills (C/C++, Python, Perl, Verilog, Verilog-AMS, WREAL). Self-motivated and enthusiastic Demonstrated ability to partner successfully with other groups to build strong cross functional relationships and meet customer needs This position requires a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering etc. with at least 5 years of industry experience. Course work in VLSI, semiconductor process, and semiconductor device physics
