Analog/GPIO/ESD Layout Summary: Layout Engineer will be working with Analog/IO/MSIP Designers in creating custom analog layout for a variety of IP types across multiple technologies. Experience with Cadence Virtuoso Custom/Analog layout platform required. Layout Engineer will be responsible for extraction and physical verification, including LVS, DRC, ERC and must have a good understanding of DRC rule interpretation and application. Must have a good working knowledge of analog layout principles, matching of devices, minimizing the impact of parasitics, and best practices for floorplanning. Job Profile: Implement layout for MSIP including GPIO and ESD mainly in 16ffc Perform physical verification including LVS, DRC, ERC and debug/cleanup to correct layout. Create floorplanning and coordinate with designers and other layout to create optimal implementation of layout for best area and performance Skillset: Strong microelectronics fundamentals and Basic understanding of Full Custom Flow. Experience with Cadence Virtuoso Custom/Analog layout platform required Good working knowledge of analog layout principles, matching of devices, minimizing the impact of parasitics, and best practices for floorplanning. Must have experience with advanced finfet technologies - specifically TSMC 16ffc. Behaviours: Proficiency in English - reading, writing, speaking. Fast Learning and positive attitude. High customer orientation, curious to learn and adapt Interaction with Team members and Customers. Flexible working hours management: during working hours and weekend support (when needed)
