Senior Logic Design Engineer
- Bangalore, Karnataka
- Permanent
- Full-time
- Ensure high quality deliverables from RTL to Physical Design
- Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results
- Create, analyze, and maintain timing constraints/SDCs
- Analyze and drive UPF solutions for low power checks
- Drive RTL to Synthesis FEV clean
- Collaborate with RTL and Physical Design team to address design feedback and drive quality
- Required Qualifications:
- MS with 5+ years of experience or BS with 7+ years of experience.
- At least 5+ years of experience applying digital design principles in SOC and/or IP development.
- Strong Static Timing Analysis background; understanding timing signoff fundamentals.
- Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus.
- Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion & demotion.
- Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints.
- Understanding in design closure challenges in power and clock domain crossings.
- Understanding reset and FIFO related design requirements.
- Preferred Qualifications
- Experience with FEV and industry standard tools such as Formality and/or Conformal
- Applied understanding of low power design principles.
- Highly Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
- Strong understanding in clock crossing techniques
- Strong understanding in IJPF (Low power intent).
- Ability to write scripts using Perl, TCI, Python etc.
- Familiarity with Industry standard interface protocols is a plus.
- Good verbal and written communication skills.