Understand the technology challenges, work with partner groups to provide CMOS Test Structure design and layout solution for N, N+1 and N+2 process technology nodes Verify integrity of the TEG design through LVS, DRC, E-simulation, and in-house verification tools Ability to drive the forums with customers to maintain high customer satisfaction. Attend necessary area meetings to understand the scope and Coordinate activities related to Scribe scheduling, design, improvement and Tape Out. Understand the Fab Quality performance of our Scribe designs Strive to continuously improve the accuracy and repeatability of our Structures Use Metrics and data to drive decisions and improve performance. Provide advice and counsel to senior management on significant technical issues related to CMOS TEG design solutions and automation. Define and lead complex and multi-disciplinary projects that are critical for SCRIBE Design solutions Strong knowledge in different families of cmos devices(Planar/Finfet) Mentor to the junior level engineers in the scribe team. Ability to understand the existing methodologies quickly and provide enhancements in quality and CT improvement. Ability to create innovative ideas to improve the process and solve the existing problems.
