Principal Engineer, Performance Modelling and Verification (Location: Noida)
Renesas Electronics
- Noida, Uttar Pradesh
- Permanent
- Full-time
- Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.
- Work closely with system architects to define high level specifications that are implementable and robust.
- Interface with verification/validation teams to ensure design quality and robustness.
- Work with various EDA vendors to deploy next generation tools
- Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
- Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
- Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies
- Responsible for developing detailed Technical SoC verification execution plans, including resource schedules, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations
- Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs.
- Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
- Participate in customer engagements assessing quality and risks
- This role requires close collaboration across global teams for resolving SoC Verification methodology alignment, the leadership role needs to be strongly integrated locally as well as globally in order to make the right trade-offs in methodology and project execution
- This role with have direct impact on product execution for business lines, responsible for schedule, cost and quality commitments in SoC verification as well as identifying key improvements and ROI across the entire development process
- Directors in IP development to plan strategic SoC Verification dependencies, roadmaps and methodologies and strategic IP innovations
- Chief Architects and Engineers for developing SoC Verification strategic roadmaps and managing execution deliverables from SoC Verification team
- Directors in implementation, RTL, DFT, Emulation to collaborate on project development plans and execution and develop common methodologies
- VP’s and directors in R&D and Business Lines to provide project status, strategic methodologies and tools.
- Degree in Electrical Engineering or Computer Science, with 15+ years of experience on IP/Sub-System Verification. Candidate should be an experienced manager with a history of leading successful SoC RTL and Verification teams.
- Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
- Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
- Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
- Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
- Good knowledge in scripting like Perl, TCL or Python is a plus
- High proficiency in Metric Driven Verification concepts, functional and code coverage.
- Expertise in directed and constrained random methodologies.
- Good knowledge of formal verification methodologies and assertions.
- Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
- Excellent written and verbal communication skill.
- Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
- Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals.
- Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
- Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.
- Must have strong track record of managing RTL design through several successful tapeouts.